For the record, the TSMC N2 node being worked on experimentally at the moment (and is expected to be more performant than Intel’s 18A) currently has over 60% yields.
We don’t have exact figures on TSMC N4 (what AMD CPUs currently use), but reporting is widely that it is “over 80%”.
For someone more in tune with the process, honest question: how is this not a failure on ASML, who makes the lithography machines? Or the company who makes the ultra pure silicon wafers? Is Intel just feeding unetchable garbage into the machines?
TSMC and Intel both use ASML lithography, but there are many many more steps than just lithography - Intel, TSMC, Samsung and other chipmakers use different processes to make the components on their chips (many of which are patented and so owned by specific parties).
These things include the physical structure of the components and wiring on the chip, how the silicon is doped and with what ions, what coatings are put on to be etched in the lithography and what coatings are applied to the etched layers, how the chips are packaged and also how multiple chips can be combined into one package.
Basically there are similarities but also hige differences between the different manufacturers, and a lot of trade secrets.
If you’re interested in this kind of thing, I’d recommend the youtube channel Asianometry - the content creator is amazing.
Thanks for the detailed and thoughtful response. I’ll definitely check out the YouTube channel you shared!
TSMC uses the same lithography and same wafers and gets working chips. It’s the fab process. Is it fixable? Idk.
I have no idea about anything at all, but part of me wants to see this be the result of some predictable, stupid mistake, like a unit conversion error or something, and another part of me wants it to be something totally unpredictable, like some unique gravitational anomaly or some latent radiation of some kind, like, something with muons.
